Method and system for regenerating amplitude and timing characteristics of an analog signal

ABSTRACT

The present invention provides a system and method for using a single  digzed component of an analog signal to be converted into a pair of digital signals used to re-establish the analog signal. A low level serial transceiver transforms a first analog signal into a first digital signal representing the complement of the first analog signal. The first digital signal is propagated through an electronic interface circuit such as a matrix switch or through some electronic circuit used to detect characteristics of the analog signal. In response to receiving the first digital signal, a logic circuit generates a second digital signal representing the analog signal, and also outputs the first digital signal. In response to receiving the first and second digital signals, a retimer generates a third digital signal comprising a series of pulses. Each of the pulses of the third digital signal is generated in response to the retimer determining that the first digital signal undergoes a positive voltage transition from one logic level to a higher logic level. The retimer also generates a fourth digital signal comprising a series of pulses. Similarly, each pulse of the fourth digital signal is generated in response to the retimer determining that the second digital signal undergoes a positive voltage transition from one logic level to a higher logic level. A second low level serial transceiver transforms the third and fourth digital signals into a second analog signal having substantially the same waveform as has the first analog signal.

STATEMENT OF GOVERNMENT INTEREST

The invention described herein may be manufactured and used by or forthe government of the United States of America for governmental purposeswithout the payment of any royalties thereupon or therefore.

BACKGROUND OF THE INVENTION

The present invention relates to the field of signal processing, andmore particularly, to regenerating amplitude and timing of an analogsignal and to reducing propagation delay of the signal.

Manchester encoding is a well-known technique in which data and dataclock components are combined into a single encoded waveform. Theencoded waveform is divided into time slots of equal duration commonlycalled data cells during each of which one binary digit (bit) ofinformation is conveyed. The state of the bit is indicated by atransition in the waveform occurring at the center or mid-cell point ofthe data cell. The direction of the transition indicates the value ofthe bit. At least one signal transition per data cell occurs, providinga component in the frequency domain centered at twice the bit occurrencerate.

The digital nature of the Manchester code provides the usualpreservation of data information in the face of communication channelcorruption by noise and other transmission effects. The timing componentof the waveform eliminates the need for two physically separatetransmission channels, as for example, one for data and one for timing.

Transmission standard, MIL-STD-1397B, Type E (NAVY), provides fortwo-way information transfer in a single bi-directional transmissionchannel. The transmission scheme has three states: logic 1, logic 0, andan idle state. The protocol of this standard imposes a frame format inwhich up to a given number of bits are transmitted as an integral unitfrom an information source on the transmission line. A "synch" bitbegins each frame. A frame may have three or more bits in addition tothe synch bit. Each frame size is variable, and the end of a frame isindicated by the presence of the idle state.

An essential element of a communication system employing the datatransmission and protocol approaches just described is an element whichis able to convert a Manchester-encoded waveform (normally a three-statesignal) to a two level digital waveform and which can convert a twolevel digital waveform into a Manchester waveform. Such an element iscommonly referred to as a "codec", which is a shortened form of the termcoder/decoder. As is conventional, codecs are important components ofdata links between computers and peripherals. Frequently, such datalinks convey information over relatively great distances, thereby oftenemploying a Manchester-encoded transmission channel. In such anapplication, a codec decodes data into a local format from theManchester-encoded format and encodes locally-formatted data into theManchester format. Usually, the decoder portion of the codec includes aretiming provision through which the received Manchester signal isimproved by reestablishing the relative timing of the two level digitalwaveform transitions.

U.S. Pat. No. 5,127,023 describes a retiming decoder/encoder ("RDE") bywhich MIL-STD 1397 Type "E" (Low Level Serial) data transmitted isretimed and converted into a more convenient format for the purposes ofswitching, etc., then reconverted back to low level serial fortransmission to the end user computer or peripheral device. The RDEconverts low level serial signals in to a pair of complementaryManchester encoded digital signals by an input transceiver. Thesesignals are next retimed and decoded into a simpler NRZ format by theRDE and conveyed through a switching matrix to the output section. Atthe output, the reverse process takes place. First, the NRZ signal isencoded back to a Manchester encoded complementary pair by the RDEencoder and sent to the output transceiver, where they are convertedback into a low level serial analog signal.

While highly successful in function, the RDE described in U.S. Pat. No.5,127,023 requires a system clock in order to synchronize the transferof data from the input to output stages of the circuit. The circuitry tosupport such synchronization results in a propagation delay and asubsequent reduction in data throughput. Additionally, the system clockincreases hardware complexity and EMI interference.

A paramount consideration in the distribution of low level serial dataor its conveyance between two communication nodes, such as a computerand a peripheral device, is that any intermediate device be astransparent as possible to minimize propagation delay. Propagation delayof the data can interfere with the system software so as to make thetransmission unworkable. As computers become faster, the data transferrate assumes critical importance. Delay in the transmission of such datacauses a reduction in the data throughput. The delay may also severelylimit the communication distance between communication nodes because anydelay adds to that already contributed to by cable length betweenequipment.

One method of reducing delay in the propagation of a data signal is todecrease the physical distance and resulting cable length betweencommunication nodes or devices. However, there are many applicationswhere this traditional solution is not practical. Therefore, there is aneed for a system and method for minimizing the propagation delay ofManchester encoded data through an intermediate electronic device, suchas a switch, in a way which maintains the integrity of the waveform(amplitude and timing) of the original encoded data.

SUMMARY OF THE INVENTION

The present invention provides a system and method for regeneratingamplitude and timing characteristics of a signal which may have incurreddistortion as a result of having been propagated through an electricalcircuit.

One aspect of the invention provides a system which includes a low levelserial transceiver for transforming a first analog signal into a firstdigital signal representing the complement of the first analog signal.The first digital signal is propagated through an electronic interfacecircuit such as a matrix switch or through some electronic circuit,which may for example, be used to detect certain characteristics of theanalog signal. In response to receiving the first digital signal, alogic circuit generates a second digital signal representing the analogsignal, and also outputs the first digital signal. In response toreceiving the first and second digital signals, a retimer generates athird digital signal comprising a series of pulses. Each of the pulsesof the third digital signal is generated in response to the retimerdetermining that the first digital signal undergoes a positive voltagetransition from one logic level to a higher logic level. The retimeralso generates a fourth digital signal comprising a series of pulses.Similarly, each pulse of the fourth digital signal is generated inresponse to the retimer determining that the second digital signalundergoes a positive voltage transition from one logic level to a higherlogic level. A second low level serial transceiver transforms the thirdand fourth digital signals into a second analog signal havingsubstantially the same waveform as has the first analog signal.

The present invention may also be characterized as a method forregenerating amplitude and timing characteristics of an analog signal.Such method includes the steps of: 1) transforming a first analog signalhaving a first waveform into a first digital signal representing thecomplement of the analog signal; 2) propagating the first digital signalthrough an electronic interface circuit; 3) generating a second digitalsignal representing the analog signal in response to receiving the firstdigital signal, and outputting the first digital signal; 4) transformingthe first and second digital signals into a first retimed digital signaland a second retimed digital signal, where the first and second retimeddigital signals correspond to the first and second digital signals,respectively; and 5) transforming the first and second retimed digitalsignals into a second analog signal having a second waveformsubstantially corresponding to the first waveform.

An important feature of the present invention is that it provides asystem and method which overcomes any timing distortion to which theanalog or its digital representation may become subjected. A significantadvantage of this characteristic is that data nodes between which datais transferred may be located further apart without risk of introducingtiming distortion in the data. Another advantage of the presentinvention is that any data propagated by way of the present invention isnot as vulnerable to corruption, thus reducing or eliminating dataerrors or even loss. The achievement of these features and advantageswill be appreciated when the following detailed description is read inconjunction with the below-described drawings.

Another advantage of the present invention is that data propagatedthrough the invention need not be subjected to propagational delayscaused by clocking of the data or by decoding/encoding conversions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system for achieving low level serialinterface enhancement embodying various features of the presentinvention.

FIG. 2 is a block diagram of a matrix switch which may be used as anintermediate electronic device in the system of FIG. 1.

FIG. 3 is a block diagram of a multiplexer group of FIG. 2.

FIG. 4 illustrates a Manchester-encoded waveform.

FIG. 5 shows a digital representation of the Manchester encoded waveformof FIG. 4, and its complement.

FIG. 6 is a data frame of a Manchester encoded waveform.

FIG. 7 is a more detailed block diagram of the retimer illustrated inFIG. 1.

FIG. 8 is a logic diagram illustrating end-of-frame detection shiftregisters and the reset generator circuit of the retimer of FIG. 7.

FIG. 9 is a logic diagram illustrating the data reshaping andsynchronization transition detecting circuit, and the clock generationcontrol circuit of the retimer of FIG. 7.

FIG. 10 is a logic diagram illustrating the frame envelope detectorcircuit and latch up detector circuit of the retimer of FIG. 7.

FIG. 11 is a set of waveform drawings illustrating various operations ofthe retimer.

FIG. 12 presents of set of waveforms showing the overall operation ofthe retimer.

Throughout the several figures, like components are referenced with likedesignations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention provides a system and method for using a singledigitized component of an analog signal to be conveyed through anintermediate device and subsequently converted into a pair of bi-leveldigital signals which are used to re-establish the original analogsignal.

An overview of a system 50 embodying various features of the presentinvention is described with reference to FIG. 1. An analog data signal53, such as a Manchester encoded data signal, is provided to atransceiver 52 which transforms the analog data signal into a digitaldata signal, "/DATA", representing the complement of the analog datasignal 53. Transceivers generating digital representations of analogdata signals and their complements are well known in the art. Forexample, in the preferred embodiment of the present invention, thetransceiver may be implemented in accordance with the teachings of U.S.Pat. No. 5,272,722, "Low Level Serial Transceiver," assigned to theUnited States of America and incorporated herein by reference. Thedigital data signal /DATA next is propagated through an intermediatedevice 54 which, for example, may be an M×N matrix switch, a repeater,or an interface monitor. After propagating through the throughput device54, the data signal /DATA is provided to a logic circuit 55 whichgenerates a digital data signal, "DATA", which represents the analogdata signal 53, in response to receiving the data signal /DATA. Thelogic circuit 55 then provides the data signals DATA and /DATA to aretimer 58 which transforms the data signals DATA and /DATA into retimeddigital data signals RDATA and /RDATA, respectively. By way of example,the logic circuit 55 may be implemented as an Intel Part No. SN74265.The retimer 58 eliminates pulse width errors which accumulate in thedata signals DATA and /DATA as a result of all the transformationsincurred by the analog data signal 53 and data signal /DATA. A secondtransceiver 52 receives data signals RDATA and /RDATA and transformsthem into an analog data signal 60 having a waveform which duplicatesthe waveform of the analog data signal 53.

As previously mentioned, the intermediate device 54 may be an M×N matrixswitch 59. Generally matrix switches are well known by those skilled inthe art. However, an example of one matrix switch particularly suited inone implementation of the present invention is described with referenceto FIGS. 2 and 3. Referring now to FIG. 2, there is shown, by way ofexample, a 16×16 matrix switch 59 comprised of 16 multiplex groupsdesignated as MUX GRP_(n), where n is a positive integer from 1 to 16,which each receive the DATA signal from the transceiver 52. The purposeof the matrix switch 59 is to direct any of the (16) input /DATA signalsto any one of (16) outputs of the matrix switch. Each multiplex groupprovides for a single output for any of the (16) inputs it receives. Theprocess of routing a signal through the matrix switch 59 begins byselecting a single multiplexer group for operation, as would be wellknown by those skilled in art. Each MUX GRP_(n) may be configured asshown in FIG. 3 to include an array of multiplexers MUX.sub.(p,q), wherep and q represent positive integers. The purpose of the multiplexers isto output a predetermined one of the inputs to the multiplexer. A firstrow of multiplexers MUX.sub.(1,1) to MUX.sub.(1,16) each receive twoinputs of the input signals /DATA₁ to /DATA₁₆, respectively, whichcomprise the composite signal /DATA. By way of example, the multiplexersMUX.sub.(p,q) may be implemented as an Intel LLS Digital To DigitalElectronic Switch, Part No. SA-2588A/FSQ-157(V). In order to select theparticular address line on which to output any particular one of theinput signals /DATA_(n), where "n" is defined above, a MUX GRP addresssignal ADDR0 selects one input of multiplexers MUX.sub.(1,1) toMUX.sub.(1,8) ; a second address signal ADDR1 selects one input ofmultiplexers MUX.sub.(2,1) to MUX.sub.(2,4) ; a third address signalADDR2 selects one input of multiplexers MUX.sub.(3,1) to MUX.sub.(3,2) ;a fourth address signal ADDR3 selects one input of multiplexerMUX.sub.(4,1). The address signals ADDRX may be generated by a computer,not shown, as would be well known by those of ordinary skill in the art.Thus, it may be appreciated that the 16×16 matrix switch 59 may be usedto switch any one of an "M" number of inputs lines to any one of "N"output lines, where "M" and "N" are each integral multiples of two. Itis to be understood that "N" and "M" are not limited to each being equalto 16, but rather may be any integral multiples of two, as for example,4, 8, 16, 32, 64, etc., required to suit the needs of a particularapplication.

In order to appreciate the present invention, a discussion of Manchesterencoded data is first presented. FIG. 4 illustrates a Manchester-encodedwaveform 10, shown, by way of example to include a frame comprising fourdata cells 1, 2, 3, and 4 which each contain an information bit. Ingeneral, the Manchester-encoded waveform 10 transitions betweensignaling states 17 and 18 around a quiescent state 19. When noinformation is transmitted, the waveform 10 enters and assumes thequiescent state 19. Each of the data cells 1-4 represent an encodedportion of the waveform 10. The first cell 1 includes a synch bit whichat a time representing the mid-cell, transitions from the relatively"high" level 17 to the relatively "low" level 18 through the quiescentlevel 19. (Hereafter, this transition will be referred to as a"negative-going" transition). In data cells 2, 3, and 4, the Manchesterwaveform, by way of example, transitions at mid-cell from level 18 tolevel 17 (hereinafter, "positive-going" transitions). In the datatransmission format for the waveform 10, negative mid-cell transitionsdenote a digital "one", and positive mid-cell transitions denote adigital "zero". FIG. 5 illustrates a pair of complementary bileveldigital data waveforms 12 and 14, which together represent the analogwaveform 10.

In the communication protocol of MIL-STD-1397B, Type E, the first bit indata cell 1 of every frame of transmitted Manchester-encoded data hasthe pattern illustrated in FIG. 4, which corresponds to an encoded "1".The first bit in data cell 1 is referred to as synch bit 11. The synchbit synchronizes the incoming waveform 10 to the operations of theterminal where it is received. For this, two transitions, indicated by21 and 22 are provided.

In the system 50, processing the Manchester waveform through thetransceiver 52 imposes two significant artifacts on the waveforms 12 and14. First, transmission through the circuitry of the system 50characteristically widens the first half of the synch bit with respectto the corresponding widths of subsequent bits. Thus, in the waveform10, the period between 21-22 of cell 1 is greater than the period 23-24of the subsequent bit in cell 2. Second, in converting the waveform 10to the complementary waveforms 12 and 14, a transceiver reduces thepulse widths of the digital waveforms 12 and 14 corresponding to thepulse widths of the analog waveform 10 following the synch bit. Thus,the width 28-30 is less than the width 23-24. These pulse width alteringeffects are referred to as "pulse width distortion".

FIGS. 4, 5 and 6 illustrate the framing feature of a communicationprotocol according to the MIL-STD-1397B. Referring to FIG. 6, theManchester-encoded waveform 42 comprises a data frame 49 ofManchester-encoded data including a synch bit 45 and a data component47. The frame 49 is separated from a following frame by an idle period51. Since MIL-STD-1397B, Type "E" requires intra-frame transitions to beseparated by no more than 100 ns, an absence of transitions for a periodgreater than 100 ns means that a frame has ended. Therefore, aninterframe idle period 51 between the end of one frame and the beginningof the a subsequent frame corresponds to the time between the lastsignal transition in the preceding frame and the positive-goingtransition in the synch pulse of one succeeding frame. Thus, in FIG. 6,the end of the interframe idle period 51 is signified by the positivetransition 48 beginning the synch bit of the following frame. Ideally,the frame signal 49 goes positive with the positive transition in thesynch bit 45 of the Manchester waveform 10 and falls at the end of theframe.

The retimer 58 retimes the pair of complementary bilevel data signalsDATA and /DATA received from the logic circuit 55 and removes the timingdistortion described above. Referring now to FIG. 12, there are shownexamples of a DATA signal 500 and a /DATA signal 502 which are providedas inputs to the retimer 58. In response to receiving DATA signal 500and RDATA signal 502, the retimer generates, by way of example, an RDATAsignal 504 and a /RDATA signal 506. The DATA signal 500 is comprised, byway of example, of a series of digital data signals, or pulses 500a,500b, 500c, and 500d which transition between a low logic level 503 to ahigh logic level 504. It is to be understood that a "low" logic levelrefers to a low voltage level and a "high" logic level refers to avoltage level higher than the low voltage level. The /DATA signal 502 iscomprised, by way of example, of a series of digital data pulses 502aand 502b shown to transition between a low logic level 505 to a highlogic level 507. The retimer 58 detects and responds to positive voltagetransitions in the DATA and /DATA signals 500 and 502. Positivetransitions satisfy the relation dv/dt>0, where "v" represents theinstantaneous voltage of the signals DATA 500 and /DATA 502, and "t"represents time.

Still referring to FIG. 12 with regard to the DATA signal 500, forexample, in response to detecting the positive transition 508 of thepulse 500a occurring at the mid-point of data cell 4, and the positivetransition 510 of the pulse 500b occurring at the midpoint of data cell3, the retimer 58 generates a series of pulses 512 and 514 comprisingthe RDATA signal 504 which transition between a low logic level 522 anda high logic 524. An important feature of the retimer 58 is that thepulses 512 and 514 have a predetermined pulse width, "W". Thus, it maybe appreciated that no matter how distorted the pulses 500a, 500b, and500c of the DATA signal 500 may become, the RDATA signal 504 generatedby the retimer 58 accurately duplicates the timing characteristics ofthe DATA signal 500 without any distortion. With reference to the DATAsignal 500 and the RDATA signal 504, by way of example, a transition toa high logic state represents a logic "0" and to a low logic levelrepresents a logic "1".

Still referring to FIG. 12 with regard to the /DATA signal 502, forexample, in response to detecting the positive voltage transition 516 ofthe pulse 502a occurring at the beginning of data cell 4, and thepositive voltage transition 517 of the pulse 502b occurring at thebeginning of data cell 3, the retimer 58 generates a series of pulses518 and 520, respectively, comprising the /RDATA signal 506 whichtransition between a low logic level 530 and a high logic level 532. Thepulses 518 and 520 have a predetermined pulse width, "V" which isgenerally, but not necessarily equal to "W". Thus, no matter howdistorted the pulses 502a and 502b of the /DATA signal 502 may become,the /RDATA signal 506 generated by the retimer 58 accurately duplicatesthe timing characteristics of the /DATA signal 502 without anydistortion. With reference to the /DATA signal 502 and the /RDATA signal506, by way of example, a transition to a high logic level, or staterepresents a logic "1" and to a low logic level represents a logic "0".

The retimer generates the retimed signals RDATA and its complement/RDATA, as well as a binary ENVELOPE signal, which are provided to thesecond transceiver 52. The ENVELOPE signal controls the output state ofthe transceiver 52, i.e., whether the transceiver is in a transmit orreceive mode.

Referring now to FIG. 7, the buffer 70 of retimer 58 receives thecomplementary binary data signals DATA and /DATA from the logic circuit55 which are denoted A0 and A1, respectively, for convenience. Thesesignals are fed to a data reshaping and synch transition detectioncircuit 72 which corrects the timing distortion of the A0 and A1signals. In the discussion following, it is to be understood that thesignals A0 and A1 have the corresponding waveforms 12 and 14,respectively, of FIG. 5.

After retiming, the A0 and A1 signals are provided as the DATA and /DATAsignals to shift registers 74 and 75, respectively, for end of framedetection. Circuit 72 also looks for the synch bit 45 in the data frame49 (FIG. 6). In response to detecting the synch bit 45, the circuit 72produces a SYNCH TRANSITION signal which initiates the overalloperations of the retimer 58. The SYNCH TRANSITION signal is fed to theregisters 74 and 75 to enable the registers to serially receive andshift the DATA and /DATA signals, respectively. Each shift register 74and 75 includes, by way of example, six serially-connected flipflops(FIG. 8) for serially shifting the DATA and /DATA signals, respectively,through the registers.

The SYNCH TRANSITION signal is also provided to a clock generation andcontrol circuit 78 which receives the output of the clock 56 and, inresponse to the SYNCH TRANSITION signal, produces a pair ofcomplementary clocks A2 and /A2. The clock signals A2 and /A2 are usedto double clock registers 74 and 75. The registers 74 and 75 seriallyshift the DATA and /DATA signals within a window of time wide enough todetect the end of a data frame.

In one preferred embodiment of the present invention, theManchester-encoded analog signal 53 has a data rate of 10 MHz and aclock rate of 10 MHz. Thus, data bit transitions will occur at 100 nsintervals at the midpoint of each data cell. The period of each datacell is also 100 ns wide. Therefore, in order to clock the DATA and/DATA signals through the registers 74 and 75, respectively, optimumclocking requires that the sampling clock edge fall at the one-quarterand three-quarter points in the Manchester data cells in order to avoidthe transition that always occurs at the midpoint. In the preferredembodiment, by way of example, such clocking may be implemented by a 20MHz clock. Optimum clocking is accomplished by the clock generation andcontrol circuit 78 which is arranged to delay the output of the firstclock pulse by a nominal period of 25 ns after being released by theSYNCH TRANSITION, which corresponds to the second transition of a dataframe. The clock generated by the circuit 78 is derived from an inputsignal generated by the clock circuit 56. Preferably, the clock circuit56 generates a free-running 40 MHz clock which is asynchronous with thedata received from the logic circuit 55. However, the speed of clock 56means that the clocks A2 and /A2 which are derived from it willnominally vary by no more than ±12.5 ns about the one-quarter andthree-quarter points of a pulse width in the data cell, and will fallwithin the first and last halves of the data cell period.

Since data bit transitions occur at 100 ns intervals about the midpointof a Manchester data cell, the test for the end of a data frame must begreater than 100 ns in order to detect a cessation of transitions. Inthe preferred embodiment of the circuit 50, the end of a data frame isdetected when a period of 150 ns (the idle period 51) transpires duringwhich no transitions in the pair of complementary binary data signals A0and A1 occur. Therefore, the shift registers 74 and 75 provide 150 nswindows of time through which the DATA and /DATA signals are seriallyshifted, respectively.

As the transitions in the data signals stop, either the DATA or /DATAsignal will remain high due to the last transition. This high level willeventually fill one of the shift registers 74 or 75. Reset generatorcircuit 76 continuously monitors the contents of the shift registers 74and 75. When the first of either register 74 or 75 is entirely filledwith high-level signals, circuit 76 will activate a RESET signal,indicating the end of the data frame. A low RESET signal causes theoperation of the clock generation and control circuit 78 to stop,placing it in a quiescent state, with clock signals A2 high and /A2 low.The low reset signal also causes the outputs of the shift registers 74and 75 go low, causing the RESET signal generated by the reset generatorcircuit 76 to go back to the high state, whereupon the retimer 58 isreset to accept a new data frame 42.

End of frame signals EF1 and EF2 generated by the end of frame shiftregisters 74 and 75, respectively, are precursors to generation of theRESET signal by the circuit 76. Signals EF1, EF2, and the RESET signalare provided to a NAND gate 82 which also receives the output of thefourth flipflop of the shift register 74 which is the retimed RDATAsignal. As long as the end of the current data frame has not beendetected, the NAND gate 82 outputs RDATA signal which is the retimed anddelayed positive-sense DATA signal input to the shift register 74. Thissignal is denoted as A7 in FIG. 7 and it corresponds to the waveform 12in FIG. 5 after retiming. A retimed RDATA signal (A8) is similarlyproduced by a NAND gate 83 which is illustrated in FIG. 8.

The frame envelope signal, denoted as A5 in FIG. 7, is produced by aframe envelope detector 84. The frame envelope detector 84 receives theSYNCH TRANSITION signal that initiates the generation of the clocks A2and /A2 and the RESET and the end of frame signals EF1 and EF2. Thesesignals are used by the circuit 84 to generate the frame envelope signalwhich is provided to the second transceiver 52.

Sometimes phase drift between the pair of complementary binary datasignals DATA and /DATA will cause a slight overlap, thereby presentingthe same level for both signals to the retimer 58. Such overlap cancause the end of frame detection circuits 74 and 75 to fail to producethe EF1 and EF2 signals. When an overlap occurs, the latch up detector86 will pulse the circuit 76 to activate the RESET signal.

Refer now to FIG. 9 for further explanation of data reshaping and synchtransition detection circuit 72 and clock generation and control circuit78 which are both also shown in the retimer block diagram of FIG. 7. Thesignals A0 and A1 which correspond to signals 12 and 14, respectively ofFIG. 5 are buffered at 70, each through a respective buffer inverter 71.The positive sense signal, A0, is fed to the CLEAR (C) port of flipflop100 and the SET(S) port of flipflop 102. The inverted signal A1 is fedto the SET port of the flipflop 100 and to the CLEAR port of theflipflop 102. The flipflops 100 and 102 are driven by the A0 and A1signals, without clocking to remove the timing distortion from therespective waveforms of signals A0 and A1. The flipflop 100 provides theretimed DATA signal and the flipflop 102 providing the retimed /DATAsignal. A NAND gate 103 has two inputs, one tied to a positive signallevel V+. The other input of the NAND gate 103 receives the invertedform of the A1 signal. Therefore, at the first negative transition ofthe inverted A1 signal corresponding to the negative-going transition atthe mid-cell point of the synch bit in a Manchester-encoded data frame,the output of the NAND gate 103 will rise. This high transition is fedto the clock input of flipflop 104. At the end of the data framepreceding the current data frame, the RESET signal will have beenactivated, clearing the flipflop 104. When a positive transitioningpulse is produced by the NAND gate 103, the V+ potential of the D inputof the flipflop 104 will cause the Q output of flipflop 104 totransition positively. For the remainder of the current data frame, theQ output of flipflop 104 will remain at a positive digital logic level.At the end of the frame, the RESET signal will once again reset theflipflop 104, causing the Q output to transition to a "zero" logiclevel, producing a SYNCH TRANSITION signal denoting the beginning of anew data frame.

In the clock generation and control circuit 78, the output of afree-running 40 MHz clock 56 is fed in inverted form to a flipflop 106and in positive form to a flipflop 108. When the SYNCH TRANSITION signaltransitions to a positive digital level at the beginning of a dataframe, the flipflops 106 and 108 will conventionally divide the 40 MHzclock by half. This division will result in the provision of a 20 MHzclock output signal at the Q output of flipflop 106, denoted as A2. Inparallel, the Q output of the flipflop 106 will produce a clock /A2,which is the complement of the A2 clock.

When the SYNCH TRANSITION signal transitions to a positive level, theflipflops 106 and 108 will operate in response to input clocks. Theflipflop 108 is driven by the positive phase of the 40 MHz clock 56,while the flipflop 106 is driven by the complement of this clock. Thephase of the clocks A2 and A2 is determined by which of the flipflops106 or 108 first receives a positive clock transition at its input afteractivation of the SYNCH TRANSITION signal. Since the period of 40 MHzclock is 25 ns, a delay of no greater than one half of the 40 MHz clockperiod will elapse before the outputs of the flipflops 106 and 108 areactive. This accounts for the nominal ±12.5 ns variation about thesampling points of the DATA and DATA waveforms.

Refer now to FIG. 8 for more detailed explanation of the shift registers74 and 75. In FIG. 8 it is understood that the shift register 75 isequivalent in all structural respects to the shift register 74. Howeverin operation, the shift register 74 shifts the DATA signal, and theshift register 75 shifts /DATA signal. In shift register 74, flipflops74a, 74b, 74c, 74d, 74e, and 74f are connected conventionally forserially shifting the DATA waveform to the NAND gate 82. The CLEAR portof each flipflop is connected to receive the SYNCH TRANSITION signal.The flipflops 74a, 74c, and 74e are clocked by the /A2 signal, while theflipflops 74b, 74d, and 74f are clocked by the A2 signal. When the SYNCHTRANSITION signal goes positive, the flipflops 74a-f will serially shiftconsecutive samples of the DATA signal to the NAND gate 82. In the shiftregister 74, the first positive transition of the /A2 clock signal willsample the DATA waveform at approximately the three-quarter point in thesynch bit (FIG. 11). Thereafter, it will alternately sample at theone-quarter and three-quarter points for each succeeding data cell. Whendata stops being input to the retimer, one or the other of the DATA or/DATA signals will remain high due to the final transition in a frame.As this high level propagates through one or the other of the shiftregisters 74 or 75, the outputs of the flipflops comprising thatparticular shift register 74 or 75 will all be high. Thus all of theinputs to either the NAND gate 110 or the NAND 111 will be high, causingthe output of the AND gate 113 to fall. The falling signal output by oneof the NAND gates 110 or 111 is denoted as an end of frame signal, withthat produced by the gate 110 denoted as EF1 and that by the gate 111 asEF2. Assuming that an input signal LATCH RELEASE is high, when one orthe other end of frame signals transitions to its low state, output ofthe AND gate 113 will fall. The output signal A6 of the AND gate 113 isthe RESET signal. A falling A6 signal signifies the end of a data frame.

Referring once again to the shift register 74, it should be evident thatthe shift register operates in a time window spanning one and one-halfdata cells (or 150 ns) of the DATA waveform. This time window issufficient to detect cessation of signaling because it will reveal theabsence of a mid-bit transition in two successive data cells.

The negative transition of one of the end of frame signals, EF1 or EF2,resets the DATA and /DATA signals output by gates 82 and 83 in advanceof the actual RESET signal. This is necessary in order to not extend thepulse width of the last bit any more than absolutely necessary after thedata stops, before RESET occurs.

As FIG. 8 illustrates, the RDATA and /RDATA signals are derived throughthe NAND gates 82 and 83 from the fourth flipflops 74d and 75d of eachof the registers 74 and 75, respectively, rather than the last. Thisreduces the throughput delay of the retimer, without affecting detectionof the end of a data frame. In this regard, the last two flipflops 74dand 74e represent the 50 ns period from the mid-cell point of one cellto the beginning of the next cell.

Refer now to FIGS. 8 and 9 for an understanding of how clock generationand data reshaping are affected by the RESET signal. When a data frameends, the flipflops 100 and 102 will have stopped transitioning and willremain in respective states determined by the last transition of thejust-ended data frame. When the RESET signal transitions negatively, itclears the flipflop 104. This causes the SYNCH TRANSITION signal to falland remain low until the negative-going transition of the synch bit inthe next frame clocks the flipflop 104. When the SYNCH TRANSITION falls,the outputs of the flipflop 106 and 108 are forced high, therebydisabling the clock output A2 and A2. The negative-going transition ofthe SYNCH TRANSITION signal is fed to the clear ports of all of theflipflops comprising the shift register 74. This presets all of the Qoutputs to zero, thereby raising the output of the NAND gate 110. In theshift register 75, the SYNCH TRANSITION is fed to the set ports of thetwo left-most flipflops in the shift register (these flipflopscorrespond in position to the flipflops 74a and 74b in shift register74) and to the clear ports of the four right-most flipflops in the shiftregister. With the shift register 75 thus preset, activation of the A2and /A2 clocks will cause the /A8 output from the NAND gate 83 toinitially start from the high state and to simulate the synch pulseleading edge. Simulation of the synch pulse leading edge restores thefirst positive-going transition at the beginning of the data frame synchbit previously excluded by synch transition detection circuit 72.

Refer to FIG. 10 for an understanding of how the ENVELOPE signal isgenerated. The frame envelope detector 84 includes two flipflops 200 and202, and a NAND gate 204. At the end of a frame, when the SYNCHTRANSITION signal is deactivated, the flipflops 200 and 202 are cleared.At the beginning of the frame, when the SYNCH TRANSITION signal isactivated, the A2 clock sequences the positive state of this signalthrough the flipflop 200 to the NAND gate 204. The other inputs to theNAND gate 204 are the two end of frame signals (EF1 and EF2) and theRESET signal. Thus, the output of the NAND gate 204 transitionspositively on the first positive-going edge of the A2 clock followingthe rise of the SYNCH TRANSITION signal. This inserts the same amount ofdelay into the positive-going transition of the ENVELOPE signal as isencountered through the shift registers 74 and 75 before the DATA and/DATA signals are available to the gates 82 and 83. When either of theEF1 or EF2 signals goes negative, the NAND gate 204 is disabled,resulting in the negative transition of the ENVELOPE signal insynchronism with the data frame.

A latch up detector circuit 86 includes an AND gate 206 and a pair offlipflops 207 and 208 clocked by the free-running CLOCK 56. As long as aPDATA signal output by the flipflop 74f, a /PDATA signal output by theflipflop 75f, and the ENVELOPE signal are not simultaneously positive,the output of the AND gate 206 is a logic low. When the output of theAND gate 206 is a logic low, the Q output of the flipflop 208 in a logichigh state. However, if all three of the inputs to the AND 206 aresimultaneously high, the output of the gate 206 will transition high,enabling the positive level at the input of the flipflop 207 topropagate through to the flipflop 208 at twice the data rate of theManchester-encoded signal. This will cause the Q output of the flipflop208 to go low, thereby disabling the output of the NAND gate 113 (FIG.8) and activating the A6 (RESET) signal by causing it to pulse low. Thefree running 40 MHz clock 56 ensures that the latch up condition will beclear before the beginning of the next data frame.

The operation of the retimer 58 is described with reference to thewaveforms represented in FIG. 11. In FIG. 11, a pair of complementarybilevel waveforms A0 and A1 are illustrated with reference to the A2 and/A2 waveforms generated by the clock generation and control circuits 78.In waveform A0, the positive transition 369 represents thepositive-going transition of the synch bit of a Manchester waveform. Theretimer 58 ignores this transition and responds, instead, to thenegative-going transition of the synch bit, which is represented by thetransitions 370a and 370b in the A0 and A1 waveforms. Since thesetransitions represent the mid-point of the synch bit, location 372represents the three-quarter point in the synch bit where initialsampling by the shift registers 74 and 75 is to take place. Recall thatthe 40 MHz clock generated by clock source 56 is free-running, and thatthe clock generation and control circuit 78 responds to the firstpositive-going edge of the free-running clock signal generated by theclock 56 that occurs after the SYNCH TRANSITION signal rises. Theasynchronous relationship between A0 and A1 and the free-running clocksignal introduces a slight variable offset between the ideal samplingpoint and the first rising edge of the A2 clock. This offset isindicated by t₀ in FIG. 11 and can vary by ±12.5 ns about theone-quarter and three-quarter sampling points.

Once the A2 and /A2 waveforms are gated on by the clock generation andcontrol circuit 78, it takes two complete cycles of A2 and /A2 topropagate the waveforms A0 and A1 through to the fourth flipflops 74d ofthe shift registers 74 and 75. Thus, at transition 372, thethree-quarter point samples of the waveforms A0 and A1 are clocked intothe first flipflops 74a of the shift registers 74 and 75 by the clockedge 376, into the second flipflops 74b by clock edge 377, into thethird flipflops 74c by clock edge 378, and into the fourth flipflops 74dby the clock edge 381. At this time, the outputs A7 and A8 transition at390 and 391, respectively, corresponding, to transitions 370a and 370b,respectively, in waveforms A0 and A1. Recall that the first twoflipflops 74a and 74b of the shift register 75 were preset by thefollowing edge of the SYNCH TRANSITION signal when the previous frameended. This positive level is clocked into the third flipflop 74c of theregister 75 by clock edge 376 and into the fourth register 74d by clockedge 377.

The ENVELOPE signal A5 is generated in response to the positivetransition of the SYNCH TRANSITION signal after a delay of one clockperiod of the A2 signal through the flipflop 200 (FIG. 10). Thus, thepositive-going SYNCH TRANSITION signal is clocked into flipflop 200 byrising edge 377 of the A2 signal and the ENVELOPE signal A5 is availablefrom the frame envelope detection circuit 84 at the output. The risingedge 395 of the ENVELOPE signal is illustrated in FIG. 11 as beingcoincident with the rising edge 377 of the A2 clock signal.

The RESET signal (waveform A6 in FIG. 11) stays high until the end ofthe frame occurs, which is indicated by a period between signaltransitions of the A0 or A1 waveforms exceeding 100 ns. The shiftregisters 74 and 75 look for the first period in excess of this period,by example, of about 100 ns, in either of the retimed data waveformsduring which no signal transitions occur. In FIG. 11, such signaltransition is shown to occur beginning with the transition 400 inwaveform A0. Since the maximum intra-frame transition period is 100 ns,the retimer 58 looks at a period via the shift register 74 and 75, whichis greater than this time. In this embodiment, the shift registers 74and 75 each inspect a 150 ns period to generate the RESET signal wheneither of these registers has positive level samples for this length oftime. Thus, when the positive level following the rising edge 402 inwaveform A7 reaches the sixth flipflop 74f in the shift register 74,only one more positive transition of the A2 clock is required to fillthe shift register with 150 ns of unvarying samples. This occurs at therising edge 404 of the A2 clock, which results in the negative pulse 336of the RESET signal and the falling edge 408 of the ENVELOPE waveformA5.

Obviously many modifications and variations of this invention arepossible in light of these teachings, and is therefore to be understoodthat the invention may be practiced otherwise than as specificallydescribed, without departing from the spirit of the claims below. Forexample, the synch bit signal transition pattern of theManchester-encoded waveform may be the inverse of that described above.That is, the first transition may be a negative-going transition and thesecond a positive-going transition. Those reasonably skilled in the artwill be able to adapt the retimer 58 as described above to respond tothe second transition as taught in this invention.

We claim:
 1. A system for regenerating amplitude and timingcharacteristics of an analog signal, comprising:first means fortransforming a first analog signal having a first waveform into a firstdigital signal representing a complement of said first analog signal,said first digital signal transitioning between a first logic level anda second logic level; an electronic interface circuit through which saidfirst digital signal is propagated; a logic circuit which generates asecond digital signal representing said analog signal in response toreceiving said first digital signal and which outputs said first digitalsignal, said second digital signal transitioning between a third logiclevel and a fourth logic level; a retimer which in response to receivingsaid first and second digital signals,generates a third digital signalcomprising a third series of third pulses, each one of said third pulsesgenerated in response to said retimer determining that said firstdigital signal transitions from said first logic level to said secondlogic level; and generates a fourth digital signal comprising a fourthseries of fourth pulses, each one of said fourth pulses generated inresponse to said retimer determining that said second digital signaltransitions from said third logic level to said fourth level; and secondmeans for transforming said third and fourth digital signals into asecond analog signal having a second waveform substantiallycorresponding to said first waveform.
 2. The system of claim 1 whereinsaid electronic interface circuit is a matrix switch having an M numberof input ports and an N number of output ports, where M and N arepositive integers.
 3. The system of claim 1 wherein said first waveformis a Manchester encoded waveform.
 4. The system of claim 1 wherein saidelectronic interface circuit is a matrix switch having an M number ofinput ports and an N number of output ports for switching any one ofsaid M input ports to any one of said N output ports, where M and N arepositive integers.
 5. The system of claim 4 wherein M and N are eachintegral multiples of two.
 6. A system for regenerating amplitude andtiming characteristics of an analog signal, comprising:first means fortransforming a first analog signal having a first waveform into a firstdigital signal representing the complement of said first analog signal;an electronic interface circuit through which said first digital signalis propagated; a logic circuit which generates a second digital signalrepresenting said analog signal in response to receiving the firstdigital signal, and which outputs said first digital signal; a retimerwhich generates a first retimed digital signal and a second retimeddigital signal, corresponding to said first and second digital signals,respectively, in response to receiving said first and second digitalsignals; and second means for transforming the first and second retimeddigital signals into a second analog signal having a waveformsubstantially corresponding to said first waveform.
 7. The system ofclaim 6 wherein said electronic interface circuit is a matrix switchhaving an M number of input ports and an N number of output ports, whereM and N are positive integers.
 8. The system of claim 6 wherein saidfirst waveform is a Manchester encoded waveform.
 9. The system of claim6 wherein said electronic interface circuit is a matrix switch having anM number of input ports and an N number of output ports for switchingany one of said M input ports to any one of said N output ports, where Mand N are positive integers.
 10. The system of claim 9 wherein M and Nare each integral multiples of two.
 11. A method for regeneratingamplitude and timing characteristics of an analog signal, comprising thesteps of:for transforming a first analog signal having a first waveforminto a first digital signal representing the complement of said analogsignal; propagating said first digital signal through an electronicinterface circuit; generating a second digital signal representing saidanalog signal in response to receiving the first digital signal, andoutputting said first digital signal; transforming said first and seconddigital signals into a first retimed digital signal and a second retimeddigital signal, where said first and second retimed digital signalscorrespond to said first and second digital signals, respectively; andtransforming the first and second retimed digital signals into a secondanalog signal having a second waveform substantially corresponding tosaid first waveform.